1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly but not exclusively to integrated circuit fabrication processes and structures.
2. Description of the Background Art
As is well known, a metal oxide semiconductor (MOS) transistor comprises a source, a drain, and a gate. The source and the drain are typically formed in a substrate, such as a silicon substrate. Dopants are implanted and activated in the substrate to form a source region and a drain region, which serve as the source and the drain, respectively. The gate is formed over the substrate between the source and the drain.
Contact structures may be formed through a dielectric layer to allow an overlying structure (e.g., an interconnect line) to make an electrical connection with the source or the drain. These contact structures are typically filled with a tungsten plug. One problem with conventional MOS transistors is that as the aspect ratio of a contact structure increases, it becomes more difficult to clean the bottom of the contact structure. It is also relatively difficult to obtain good step coverage when depositing a liner on the sidewalls and bottom of a contact structure that has a high aspect ratio.